1. Field of the Invention
This invention relates to integrated circuit fabrication, and, more particularly, to microelectronic topographies incorporating memory cells and transistors and methods for fabricating such topographies.
2. Description of the Related Art
Unless specifically designated as prior art, the information described below is not admitted to be prior art by virtue of its inclusion in this Background section.
Memory circuits can be used to store and retrieve large quantities of electronic information. These circuits typically store each separate bit of information in storage elements called memory cells. Consequently, the capacity of a memory circuit is often described in terms of the number of bits that a circuit can store. In addition, memory circuits are often classified as being either volatile or non-volatile. Generally speaking, volatile memory circuits contain memory cells that cannot retain information for a substantial amount of time if the power supply is interrupted; non-volatile memory circuits contain memory cells which can retain information for a substantial amount of time if the power supply is interrupted.
Non-volatile memory circuits are generally structured as read-only memory ("ROM"), a memory configuration in which data retrieval time is relatively short but data entry time is relatively long (if data entry is possible at all). Masked ROMs, generally referred to only as ROMs, are read-only memories into which data is entered during manufacturing and that cannot be subsequently altered. Conversely, programmable ROMs ("PROMs") allow entry of data after manufacturing is complete. Several technologies may be used to form non-volatile memory circuits, including bipolar or metal oxide semiconductor ("MOS") technologies. Examples of MOS PROM technologies include erasable programmable ROM ("EPROM"), electrically erasable programmable ROM ("EEPROM"), and flash memory EEPROM ("FLASH EEPROM").
Non-volatile MOS PROMs may be configured using a variety of different designs. Some of the more widely used designs for such PROMs include floating gate tunnel oxide ("FLOTOX"), textured polysilicon, metal nitride oxide silicon ("MNOS"), and EPROM--tunnel oxide ("ETOX") designs. The particular design used for a cell may determine the manner by which the cell stores charge, as well as how the cell is programmed or erased. For example, FLOTOX EEPROM memory cells are generally programmed (moving electrons into the floating gate) by biasing the control gate, and such memory cells are generally erased (moving electrons out of the floating gate) by biasing the drain. Conversely, MNOS memory cells store charge in discrete traps within the bulk of a nitride layer formed above a thin oxide layer. Programming and erasure of such cells are accomplished by inducing electron tunneling between the nitride bulk and the substrate.
FIG. 1 illustrates a FLOTOX EEPROM memory cell according to a conventional design. The FLOTOX cell includes a relatively thin tunneling oxide 102 interposed between a doped polysilicon floating gate 104 and a silicon substrate 100. Tunneling oxide 102 is typically thermally grown upon substrate 100 to a thickness of less than, for example, 100 angstroms. The FLOTOX cell further includes an interpoly oxide 106 arranged upon floating gate 104 and underlying a doped polysilicon control gate 108. Fabrication of the FLOTOX cell may involve forming these layers above silicon substrate 100 and then etching away portions of the layers not masked by a patterned photoresist layer to form the stacked structure shown in FIG. 1. A heavily concentrated dopant distribution that is self-aligned to the opposed sidewalls of the stacked structure may then be forwarded into substrate 100 to form source and drain regions 110 and 112, respectively. An oxide layer 114 may be thermally grown upon the periphery of the stacked structure and upon exposed regions of substrate 100. Due to exposure to thermal radiation during this process, the impurities within source and drain regions 110 and 112 undergo lateral migration toward the channel region underneath tunneling oxide 102, resulting in the configuration depicted in FIG. 1.
In subsequent processing, control gate 108 may be coupled to a word line conductor and bit line conductors can be formed within contact windows of oxide layer 114 for contacting drain region 112. Floating gate 104 can then be programmed by grounding source and drain regions 110 and 112 and applying a relatively high voltage to control gate 108. During programming, electrons from the substrate pass through tunneling oxide 102 to floating gate 104 by a tunneling mechanism known as Fowler-Nordheim tunneling. As more electrons accumulate in floating gate 104, the electric field is reduced and the flow of electrons to floating gate 104 decreases. Programming of the memory cell is performed for a time sufficient to build up a desired charge level on the floating gate. Discharge of floating gate 104 to erase the cell can be achieved by grounding control gate 108, floating gate 104, and source region 110, and then applying a relatively high voltage to drain region 112.
In summary, both programming and erasure of FLOTOX EEPROMs, as well as other types of conventional memory cells, involve the transfer of electrons to and from a semiconducting substrate. More specifically, electron transfer in such conventional memory cells often occurs between junctions (e.g., source region 110 and drain region 112) and a conductive gate (e.g., floating gate 104). Consequently, these conventional memory cells must be formed upon and within a semiconductor substrate; that is, in the surface plane of the semiconductor substrate. Typically, the semiconductor substrate is a single-crystal silicon wafer.
Unfortunately, single-crystal silicon wafers have a limited amount of surface area available for the formation of memory cells. One reason for the limited surface area is that the diameter of the silicon wafers used in integrated circuit manufacture is often restricted by equipment concerns or other factors. Because FLOTOX-type conventional memory cells are formed in the surface plane of a wafer, the number of such cells that can be formed on the wafer will be limited to the available wafer surface area. Furthermore, the junctions necessary for FLOTOX-type memory cells occupy even more of the valuable wafer surface area. Consequently, to achieve a particular storage capacity conventional memory circuits are often formed on larger chips than might otherwise be desired. Greater chip size, of course, reduces the number of chips that can be obtained from a wafer of a given diameter, and thus can increase the cost of each chip fabricated from the wafer.
The limitations of conventional memory cells are also problematic when trying to implement such cells as on-chip memory for microprocessors. Current microprocessors typically include memory cells on the same chip as the logic circuitry (e.g., to act as a high-speed cache); memory cells used in such a manner are often referred to as on-chip memory. On-chip memory is typically provided using conventional memory cell designs (such as those discussed above) in which the memory cells are located in the surface plane of a silicon wafer. The conventional MOSFET transistors used in the logic circuitry of the microprocessor conduct current between junctions formed in the silicon wafer, and as such are also formed in the surface plane of a silicon wafer.
The need to place conventional transistors and memory cells on the surface plane of the same silicon wafer necessarily limits the maximum number of each device type that may be included in a given chip area on the wafer. As a result, the size of chips that incorporate significant on-chip memory must often be undesirably increased to accommodate a certain quantity of memory cells while still allowing sufficient space for the desired number of transistors. This increase in chip area, as noted above, typically results in a higher cost for the final microprocessor. Moreover, the present trend toward increased quantities of on-chip memory only exacerbates this problem.
Furthermore, placing transistors and memory cells on the wafer surface plane can complicate the integrated circuit fabrication process. For example, FLOTOX type memory cells include, as shown above, stacked layers of polysilicon separated by oxide layers. Therefore, when deposited or grown layers are etched to form such memory cells, a stacked etch must be performed that passes through multiple layers of polysilicon and oxide. MOSFETs, however, typically only include one layer each of polysilicon and oxide, and thus require a different and shorter etch process than do FLOTOX memory cells. Since the etch processes for conventional memory cells and transistors may be substantially different, the need to accommodate the different configurations and thicknesses of the structures when both types are present on the surface can complicate the fabrication process. Given the need for high accuracy in integrated circuit manufacturing, and in particular with the lateral dimensions of transistors, this increased complexity can undesirably affect the final integrated circuit.
In addition, transistors and memory cells often have different process condition requirements, and the presence of both on the same surface plane can prevent the optimal fabrication of either. For example, the total amount of thermal energy to which a device is exposed during fabrication is often tracked using a term called the thermal budget. The thermal budget for a device may be calculated as simply the product of the temperature of a processing step and the length of time for which the processing step maintains that temperature, for all processing steps to which a device is exposed during its fabrication. The optimal thermal budget for memory cells and transistors, though, may differ significantly: For example, the ideal post-doping anneal temperature for memory cells can be much higher than that for transistors.
In an attempt to accommodate the requirements of both device types, anneals in such situations are often done at a temperature below what would be optimal for the memory cell and above what would be optimal for the transistors. In other words, the ideal anneal conditions for both device types are often compromised by presence of large numbers of both devices types on the wafer surface plane. As might be expected, this situation can hinder the fabrication of an optimally configured integrated circuit.
Finally, single-crystal silicon wafers are relatively expensive--particularly when compared to wafers made from other materials such as ceramics. The higher cost of single-crystal silicon wafers largely stems from the exacting nature of their fabrication process. Great care must be taken during wafer fabrication if electronic grade silicon wafers with a desired purity and crystal orientation are to be obtained, and the demanding requirements of silicon wafer fabrication contribute substantially to the relatively high cost of single-crystal silicon wafers. But since most conventional memory cells and transistors are designed to be fabricated in the surface plane of a single-crystal silicon wafer, the purchase of such wafers cannot be avoided as long as manufacturers are dependent on conventional transistor and memory cell designs.
Therefore, it would be desirable to develop memory cells and transistors that are not required to be located in the surface plane of a single-crystal silicon substrate. It would also be desirable to design an integrated circuit that incorporates such devices and thus does not require the use of single-crystal silicon, or any other semiconducting material, as a substrate. It would further be desirable to create an integrated circuit that has both memory cells and transistors but does not require both device types to be arranged within the same plane. An integrated circuit so configured could be fabricated at reduced cost and with less complicated processing techniques.